Cortex-A73 is a dual issue out-of-order core. It doesn't use a ROB, and doesn't care about NOPs. At all!

The "slot-based" mechanism can reorder up to 96 instructions. This is low compared to modern cores, but within the range of its time.

The (small) speculative register files is the greater bottleneck, and one should expect that A73 would usually be able to reorder up to only 76 instructions.

Cortex-A73 has 7 execution ports. There are two 128-bit NEON ports for integer instructions and two ALU ports. Also included within is two 64-bit FP ports on top of the integer NEON ports.

Cortex-A73 can load up to 16 bytes per cycle, but real bandwidth measurements shows a lower result. (About 13.4 bytes per cycle.)

FMA latency is reduced from 8 to 7 cycles. It can do one 128-bit FMA per cycle, or two 64-bit FMAs per cycle.

There's an inherent limitation of 1.5 IPC for 128-bit vector operations. This is due to the register file being 6R3W, and the read paths are all 64-bit even for 128-bit instructions [speculation, citation needed].

Cortex-A73 can pull at a rate of 11GB/s from main memory, as mentioned in previous articles. Compared to high-performance cores of the 2020s, A73 falls short but is slightly better than the best A55 implementation (ref: Genio 1200).