hypothetical chip btw

tsmc n2

die area 400mm2

3072 A55 cores at 2 ghz

tdp about 150-250w

compute

24 tflops fp64

48 tflops fp32

96 tflops fp16

192 tops int8

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this chip has 96MB of ultra high bandwidth memory known as "L1 cache"

bandwidth up to 48tbps

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