title

also spacemit take notes since n2 can do 3.2ghz btw

spacemit upgraded from x100 (intel core/2) to x200 (haswell) btw... im waiting for their x300 to be finally catching up to lion cove... just make a 10-wide risc-v god-core that can clock up to 4.0 ghz*

*arm already did that with the x925/c1u btw

also p sure spacemit cheats a fair amount with 462 and simulated the results LOL... credibility = 0

1. fft
2. sử dụng immintrin.h
3. 6 chữ
4. 7 chữ
5. 6 chữ
6. 7 chữ
7. hld
8. smawk
9. fast matrix mult
10. bitwise convolution (F2^64)
11. subset convolution
12. mobius transforms
13. multi dimensional data structures
14. kookeudas
15. aho corasick
16. suffix tree
17. dp x2+1 trick
18. alien trick
19. tree decomposition width 2
20. online mst tree
21. sum of multiplicative function
22. graph block decomposition
23. block cut tree
24. persistent treap
25. Lycoris Radiata (Hard Version)
26. dp open close trick
27. dp connected components
28. cdq dnc
29. virtual tree
30. link cut tree

kiến thức nâng cao:

1. 2 con trỏ
2. rmq
3. dp trên cses (hầu hết các bài)
4. dp dnc
5. nhập xuất dữ liệu
6. euler tour
7. lý thuyết đồ thị
8. suffix array, trie

as such here's obvious facts

9000+ has 64k of l1i/d cache per core. there's some unofficial info at reptdoc.netlify.app. weirdly how in my testing seems like only x2 gets slc access or big l3 access...

a510,a710,x2 information you can search chipsandcheese.

a510 is 2x128b shared between two cores. a710 is 2x128b. x2 is 4x128b. a510 emulates bf16 support using fp32.

gpu is g710 mp10 at 955mhz ~ 1.2 tflops.

v1

cortex-x1 with 256b sve. new feature.

8 wide core w 256 entry rob

v2

cortex-x3

8 wide core w 320 entry rob

v3

cortex-x4

8 wide core w 384 entry rob

v3ae

cortex-x4 with 2 vector ports

n1

a76

4 wide core w 128 entry rob

n2

a710

5 wide core w 160 entry rob (4 wide decode)

n3

a725

5 wide core w 224 entry rob, uop cache removed

e1

a65!!! GOAT!!!

2 wide core with 40 entry rob

e2

a510 (e-waste)

e3

a520 (e-waste)

curacao vs brazil: curacao wins

mesi vs rolando: i think mesi have 95% chance to win

c1 ultra: 10/10 (baseline)

x2: 8/10

x1: 7.5/10

a78: 7/10

a710: 6.5/10

a76: 5.5/10

a73: 4.5/10

a510: 4/10

a55: 3.5/10

a53: 10/10*

a35: 3/10

*Actually 3.5/10, BUT the a53 was my whole life in 2017-2022. the a53 truly carried all of my experiences, memories, etc... without the a53 and the exynos 7870, i might be a completely different creature.... possibly the core that i lived the most with...

chắc là do

1 là newbie trong thời đại này là khá có vấn đề

bạn luyện tập đủ trò mà vẫn k làm đc 4 bài Div 3

thì nên xem lại

kể cả trong thời đại cheater thì làm 4 bài Div 3 nhanh vẫn giúp bạn thoát kiếp newbie

chúng ta quay lại Div 2

uh thì giờ thì làm AB div 2 có thể không giúp bạn thoát kiếp newbie vì quá nhiều cheater

NHƯNG

đó không phải là lí do để bạn càu nhàu về việc bạn là newbie

cách đơn giản nhất là làm ABC

gần như bạn làm ABC với pen k quá lớn là thoát kiếp newbie

nếu làm cực nhanh có thể lên S hoặc E

lưu ý: thời đại làm 4 bài Div 3 mà đc > newbie perf có thể sắp kết thúc do 2 lí do sau.

4 bài đầu đã quá dễ. D có thể chỉ 1200 thay vì 1500 (thường thấy).

Nhiều cheater. cái này thì k nói vì đến div 1 + 2 cx bị tình trạng này.

nên bạn phải làm đc 5 bài

nma 5 bài đầu Div 3 có gì

chặt nhị phân và tham lam

k cần dp luôn

cx giống như ABC div 2 vậy

"An ounce of honest data is worth a pound of marketing hype" - SPEC

The "marketing hype" in question:

Now, since I want to do a fair comparison between something that may resembles the C86-4G and an Intel processor, here's the details if I ever got a chance at it:

1. System configuration.

All processors are kept at stock settings and is configured so that no thermal throttling is detected during operation.

2. Testing procedure.

SPEC CPU 2006 will be the benchmark of choice. The testing procedure is as follows:

Compilation flags:

Optimization: -Ofast -fno-unsafe-math-optimizations -flto=<n_cores> -march=<march> -fomit-frame-pointer.

Portability: -DSPEC_CPU_LP64 -Wno-error=template-body (both base/peak).

For which the options are as follows:

For PGO runs, PGO options are enabled as follows:

PASS1_CFLAGS = -fprofile-generate
PASS1_CXXFLAGS = -fprofile-generate
PASS1_FFLAGS = -fprofile-generate
PASS1_LDFLAGS = -fprofile-generate
PASS2_CFLAGS = -fprofile-use
PASS2_CXXFLAGS = -fprofile-use
PASS2_FFLAGS = -fprofile-use
PASS2_LDFLAGS = -fprofile-use

Options such as bindN (N < n_threads) are configured so that bindN for N < n_cores maps to the physical threads.

Now, the testing procedure starts:

First, for SPEC06 STint, the testing procedure is as follows:

Launch base run and basePGO (as peak) run as above with 1 iteration.

Now, the peak tuning is generated by determining the effects of PGO on execution times (win/loss). After the PGO determination step for the peak tuning has been done, we do a full 3-iterations run and report the base/peak result.

For SPEC06 MTint, the testing procedure is as follows:

Launch base run and basePGO (as peak) run as above with 1 iteration, setting the number of copies to n_threads.

Next, launch the same configurations, but instead of setting the number of copies to n_threads, set it to n_cores.

Now, the peak tuning is generated by determining the effects of PGO and SMT on execution times (win/loss). After the PGO/SMT determination step for the peak tuning has been done, we do a full 3-iterations run and report the base/peak result.

All reported files for the final 3-iterations runs are made public (PDF, HTML, raw, flags, etc.), and the result is aggegrated to the tables as follows:

One can also plot graphs based on the test results.

The steps above should be simmilar for SPEC06 ST/MTfp scores, but optimization/portability options might need a change.

in internal testing skylake is already crushing 16 Specint2K6/Ghz just by replacing the 462.libquantum compiler.

462.libquantum is in the situation of 072.eqntott in Spec89, where it's obsolete by modern standards.